The present invention relates to logic gate oscillators and, more particularly, to monolithic integrated circuit logic gate oscillators in which selected output signal portions can be directed to occur at the oscillator output in synchronizm with an input signal feature.
Various computer system organization schemes have been used in efforts to enhance one or more aspects of the system. One such organization used to enhance the operational rapidity of such a system is based on having a dual port random access memory with one port thereof connected to the central processing unit and the other port connected to a peripheral or a buss connecting several peripherals or the like. Such an arrangement for providing direct access to the memory for both the central processing unit and the peripheral can increase operational rapidity while reducing the supervisory activities of the central processing unit.
At certain times during operation, the central processing unit will have a need to determine the status of the contents of the dual port memory. This should be done at a time when the contents of that memory are not in the process change as otherwise the central processing unit may reach a determination of contents status which is in error because some changes will have been completed and some won't at the time of the determination.
As a result, provision is often made in the system for a "flag" indicator which the central processing unit can check against, this flag indicator providing an indication of whether the dual port memory is in the process of either having its contents altered or having its contents retrieved.
One arrangement for operating the flag indicator is to have it receive the output signal of an oscillator which alternates between a pair of logic states one of which will place the flag indicator in an "enable" state and the other of which will place the flag indicator in an "inhibit" state. However, the peripheral unit or units connected to one port of the dual port random access memory and the central processing unit connected to the other port are likely to have considerably different clock frequencies providing the time bases for the operation of these devices. Thus, there must be an arrangement provided for the oscillator to have one logic state or the other in selected cycles of its output signal synchronized with these clock signals.
As a result, there is a need for an oscillator which can have a selected portion of selected cycles in its output signal waveform provided at its output in synchronizm with selected features occurring in the clock signals provided by both the central processing unit and the peripheral or peripherals. Further, such an oscillator must be operable in a monolithic integrated circuit to be suitable for use in such a computer system.